This invention relates to a control apparatus for a plurality of memory units installed in a data processing system (hereunder referred to simply as a "DP system").
A prior art DP system of the type described includes a master memory unit currently in operation and a spare memory unit for future use. A hardware failure in a program storage area of the master memory unit results in a program error in an operating system (or OS) which is adapted to control the entire system. In response to the program error, the execution of the program is terminated. Then, the foiled master memory unit is logically cut off from the rest of the system and the terminated program is transferred to the other memory unit. A significant amount of time is consumed for the transfer of the program. The execution of the transferred program is retried and the system as a whole continues its operation. The data stored in the master memory unit include OS information, in addition to the normal program. Hence, a system-down condition is unavoidable once the master memory unit storing the OS information has a hardware failure. This will have a critical influence on the whole system particularly when the DP system is applied to an online system with a high requirement for reliability. In light of this, where a hardware failure is of the intermittent nature, practising the program transferred to the other memory unit is retried. Where a hardware failure is not of the intermittent nature but is constant, a system-down condition cannot be avoided even though the retry operation may be performed. To eliminate the system-down condition, there is proposed in Japanese Laid Open Patent Application No. 80936/1974 a DP system which causes first and second memory units into parallel operation by simultaneous access. In this system, a read cycle and a write cycle are designed identical to each other to maintain full continuity of operation of the system. When the system detects a hardware failure in response to a status signal during a read mode operation, the data transmission from the failing memory unit to a processor must be switched to that from the other memory unit. A time period for this switching action is selected in proportion to the maximum width of data to be read and shorter than the period of system control clock pulses. Accordingly, since the read cycle is made longer in proportion to the data width, the write cycle also becomes longer resulting in a significant decrease in the processing rate.